This is a greater than 7 to one reduction in the update time. It is found that the FPGA rotor position Estimator with a 5MHz clock can update its rotor position estimate every 7s compared to an update time of 50s for a TMS320C6701-150 DSP implementation using a commercial DSP board. The performance of the FPGA based SRM rotor position estimator in terms of calculation time is compared to a digital signal processor (DSP) implementation of the same position estimator algorithm. The experimentally generated output is validated by comparing it with simulation results from a Simulink model of the Estimator. This circuit is implemented on a Xilinx Virtex XCV800 FPGA system. The Estimator and Commutator design is coded using Verilog HDL and is simulated using Xilinx tools. The estimated rotor position is given as input to the Commutator circuit, also implemented in the FPGA, to determine when torque-producing currents should be input in the SRM phase windings. The term 'gate level' refers to the netlist view of a circuit, usually produced by logic synthesis. This thesis uses Field Programmable Gate Array (FPGA) technology to implement a method to estimate the SRMs rotor position using the inverse inductance value of the SRMs phases. In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. Rotor Position information is essential in the operation of the Switched Reluctance Motor (SRM) for properly controlling its phase currents. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.